Memory devices conventionally include arrays of bit cells that each store a bit of data. Each data bit can represent a logical zero (“0”) or a logical one (“1”), which may correspond to a state of the bit cell. During a read operation of a selected bit cell, a voltage level close to ground may be representative of “0” and a relatively higher voltage level may be representative of “1”. Bit lines are coupled to various bit cells in the memory array and the bit lines couple the bit cells to other components used in read/write operations.
Magnetoresistive random access memory (MRAM) is a non-volatile memory technology where data is stored based on magnetization polarities of bit cells. In contrast to conventional RAM technologies which store data as electric charges or current flows, MRAM uses magnetic elements. A magnetic tunnel junction (MTJ) which is conventionally used as a storage element or bit cell for MRAM technology, can be formed from two magnetic layers, each of which can hold a magnetic moment, separated by an insulating (tunnel barrier) layer. Conventionally, the fixed layer is set to a particular polarity. The free layer's polarity is free to change to match that of an external magnetic field that can be applied. A change in the polarity of the free layer will change the resistance of the MTJ bit cell. For example, when the magnetization polarities are aligned or “parallel,” a low resistance state exists, which corresponds to a logical “0”. When the magnetization polarities are not aligned or are “anti-parallel,” a high resistance state exists, which corresponds to a logical “1”.
Thus, an MRAM or MTJ bit cell has a resistance value based on whether the bit cell represents a logical zero (“0”) or a logical one (“1”). Specifically, the resistance of the bit cell (RDATA) relates to the data stored in the bit cell. For the same or constant current flowing through the bit cell, if the value of RDATA is high relative to a reference resistance (RREF), then a relatively high voltage will appear across the bit cell, representing a logical “1”. If the value of RDATA is low relative to RREF, then a relatively low voltage will appear across the bit cell, representing a logical “0”. The difference between the voltage across RDATA (VDATA) and the voltage across RREF (VREF) therefore indicates the logic state of the bit cell (ΔV1=VDATA−VREF).
Thus, in order to write a logical “0” or a logical “1,” corresponding write currents are passed through the MTJ bit cell to effect a corresponding alignment of the free layer and the fixed layer, or in other words to program the MTJ bit cell to the corresponding resistance state.
For reading the bit cell, a sensing circuit is conventionally used to determine the differential voltage ΔV1 and a sense amplifier is used to amplify the differential voltage ΔV1 to an amplified voltage ΔV2. The sense amplifier's output is used to determine or read the logical state of the bit cell. As shown in FIG. 1, read circuit 100 includes a sense amplifier 110 comprising a pair of cross-coupled inverters formed by two p-channel metal oxide semiconductor (PMOS) transistors M1 and M2 and two n-channel metal oxide semiconductor (NMOS) transistors M3 and M4. This cross-coupled inverter pair resembles a latch used to store a digital value, and as such, is referred to as a latch circuit or a latch. Due to process variations, the latch in the sense amplifier 110 may develop an offset voltage known as a “latch offset voltage” or simply, an “offset voltage” of the sense amplifier, which will be explained below.
As shown in FIG. 1, PMOS transistor M1 and NMOS transistor M3 are coupled in series between a supply voltage (via a PMOS transistor) and ground (via a NMOS transistor, or footer transistor TF). Between transistors M1 and M3 is Node A. Transistors M2 and M4 are likewise coupled in series between a supply voltage (via the PMOS transistor) and ground (via the NMOS transistor. Between transistors M2 and M4 is Node B.
Nodes A and B are connected to the sensing circuit 120, which will now be explained. The sensing circuit includes a load transistor T7 coupled to a degeneration transistor T9 and a clamping transistor T3 coupled to Node A and to a first multiplexer transistor T5 which is connected to the bit cell (represented by variable resistor RDATA). The sensing circuit 120 also includes another load transistor T8 connected to degeneration transistor T10 and clamping transistor T4 connected to Node B and to a second multiplexer transistor T6, which is connected to a reference cell (represented by variable resistor RREF).
Load transistors T7 and T8 are diode connected. Clamping transistors T3 and T4 are controlled by the voltage VCLAMP, which is a clamp voltage used to control the flow of current through the bit cell and the reference cell. Multiplexor transistors T5 and T6 are controlled by VMUX, which is a control signal used to select the bit cell (and reference cell) during a read operation, from other bit cells in the memory array that comprises the bit cell. In a first phase, footer transistor TF is turned ‘off’ and VMUX and VCLAMP are high, causing the multiplexer transistors and clamping transistors to be turned ‘ON’. As a result, current flows from the supply voltage VDD through both RDATA and RREF. Accordingly, voltages VDATA and VREF develop at nodes A and B, respectively. The difference between VDATA and VREF represents a differential voltage ΔV1.
In a second phase, the multiplexer transistors T5 and T6 are shut off and footer transistor TF is turned on, which brings the sense amplifier into operation. If RDATA has a higher resistance value than RREF (representing a logical “1”), then VDATA will be higher than VREF, and ΔV1 will be positive at the end of the first phase. If RDATA has a lower resistance value than RREF (representing a logical high “0”), then VDATA will be lower than VREF, and ΔV1 will be negative at the end of the first phase.
In a scenario where ΔV1 is positive, PMOS transistor M2 will pass relatively less current than PMOS transistor M1, and NMOS transistor M4 will pass relatively more current than NMOS transistor M3. As a result, the voltage on Node B (VREF at the beginning of the second phase) will drop toward ground, and the voltage on Node A (VDATA at the beginning of the second phase) will rise toward supply voltage VDD. The resulting voltages at Node A and Node B are shown as VOUT-A and VOUT-B, respectively, which are outputs of the sense amplifier. The difference between VOUT-A and VOUT-B represents a differential voltage ΔV2. In a scenario where ΔV1 is negative, the opposite will happen. In particular, the voltage on Node A will drop toward ground, and the voltage on Node B will rise toward supply voltage VDD 
In an ideal sense amplifier, if ΔV1 is positive at the end of the first phase, then ΔV2 will be relatively more positive at the end of the second phase. Likewise, if ΔV1 is negative at the end of the first phase, then ΔV2 will be relatively more negative at the end of the second phase. However, as previously mentioned, a problem can arise due to transistor mismatches resulting from, for example, process variations. Transistor mismatches arise when two transistors have parameters that are intended to be equal, but are in practice unequal. A threshold voltage (VTH) of the transistor, for example, is a voltage that, if applied to a gate of the transistor, will cause current to flow between the source and drain. If the threshold voltages of transistors M1 and M3 do not match the corresponding threshold voltages of M2 and M4 of the sense amplifier 110, then an offset voltage occurs, where the offset voltage VOS of the sense amplifier 110 may be created between Node A and Node B. If the offset voltage VOS diminishes the voltage difference ΔV1, then ΔV1 will not properly act upon on the respective gates of transistors M1, M2, M3, and M4. In such a scenario, the sense amplifier 110 of circuit 100 will fail to correctly generate an amplified voltage difference ΔV2 as expected, and the bit cell will not be read correctly.